29 lines
382 B
Verilog
29 lines
382 B
Verilog
module negative_genvar;
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wire signed [3:0] value[-7:7];
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genvar i;
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for (i = 7; i >= -7; i = i - 1) begin:genloop
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assign value[i] = i;
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end
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integer j;
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reg fail = 0;
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initial begin
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#0;
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for (j = -7; j <= 7; j = j + 1) begin
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$display("%d", value[j]);
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if (value[j] !== j) fail = 1;
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end
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if (fail)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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