60 lines
1.7 KiB
Verilog
60 lines
1.7 KiB
Verilog
//
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// Copyright (c) 2001 Stephan Boettcher <stephan@nevis.cloumbia.edu>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// Validates Non-blocking assignment propagation
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// $Id: nblkpush.v,v 1.2 2005/07/07 16:25:20 stevewilliams Exp $
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// Update: This test has a race in it that makes it not valid. The
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// assumption that a blocking assign will push through the continuous
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// assignment before the thread doing the assign is allowed to advance
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// is not valid. This test only passes Verilog XL. Every other tool,
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// commercial or otherwise, seems to FAIL this test. Therefore, this
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// test should not be relied on.
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module test;
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reg a, b, c, d;
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wire ab = a & b;
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wire abc = ab | c;
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wire abcd = abc & d;
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initial
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begin
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a = 0;
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b = 1;
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c = 0;
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d = 1;
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#1;
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a = 1;
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if (abcd === 1)
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begin
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$display("PASSED");
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$finish;
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end
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$display("FAILED ab=%b, abc=%b, abcd=%b", ab, abc, abcd);
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#1;
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if (abcd === 1)
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$display("abcd value changed late");
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else
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$display("abcd value still wrong");
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end
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endmodule
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