93 lines
2.0 KiB
Verilog
93 lines
2.0 KiB
Verilog
module test ;
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wire a;
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reg sel,in0, in1;
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reg error;
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assign a = sel ? in1 : in0 ;
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initial
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begin
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error = 0;
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#1;
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sel = 0;
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in0 = 0;
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in1 = 0;
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#1;
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if(a !== 0)
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begin
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$display("FAILED - (1) Mux error sel=0, in0=in0=0 yet out != 0");
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$display("sel=%b,in0=%b,in1=%b,out=%b",
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sel,in0,in1,a);
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error = 1;
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end
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#1;
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in0 = 1;
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#1;
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if(a !== 1)
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begin
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$display("FAILED - (2) Mux error sel=0, in0=1,in1=0 yet out != 1");
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$display("sel=%b,in0=%b,in1=%b,out=%b",
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sel,in0,in1,a);
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error = 1;
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end
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#1;
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sel = 1;
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#1;
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if(a !== 0)
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begin
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$display("FAILED - (3) Mux error sel=1, in0=1,in1=0 yet out != 0");
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$display("sel=%b,in0=%b,in1=%b,out=%b",
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sel,in0,in1,a);
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error = 1;
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end
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#1;
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in1 = 1;
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#1;
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if(a !== 1)
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begin
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$display("FAILED - (5) Mux error sel=1, in0=1,in1=1 yet out != 1");
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$display("sel=%b,in0=%b,in1=%b,out=%b",
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sel,in0,in1,a);
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error = 1;
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end
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#1;
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in0 = 0;
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#1;
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if(a !== 1)
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begin
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$display("FAILED - (6) Mux error sel=1, in0=0,in1=1 yet out != 1");
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$display("sel=%b,in0=%b,in1=%b,out=%b",
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sel,in0,in1,a);
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error = 1;
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end
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#1;
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in1 = 0;
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sel = 1'bx;
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#1;
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if(a !== 0)
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begin
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$display("FAILED - (8) Mux error sel=X, in0=0,in1=0 yet out != 0");
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$display("sel=%b,in0=%b,in1=%b,out=%b",
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sel,in0,in1,a);
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error = 1;
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end
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#1;
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in0 = 1;
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in1 = 1;
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sel = 1'bx;
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#1;
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if(a !== 1)
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begin
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$display("FAILED - (9) Mux error sel=X, in0=1,in1=1 yet out != 1");
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$display("sel=%b,in0=%b,in1=%b,out=%b",
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sel,in0,in1,a);
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error = 1;
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end
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if(error === 0)
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$display("PASSED");
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end
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endmodule
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