90 lines
1.9 KiB
Verilog
90 lines
1.9 KiB
Verilog
//
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// Copyright (c) 2002 Steven Wilson (steve@ka6s.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW: Synth of basic reg form
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//
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//
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module basicreg ( clk, d, q);
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input clk, d;
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output [2:0] q;
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reg [2:0] q;
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(* ivl_synthesis_on *)
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always @(posedge clk)
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begin
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q[0] <= d;
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q[1] <= d;
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q[2] <= d;
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end
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endmodule
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module test ;
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reg clk, d;
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wire [2:0] q;
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basicreg u_reg (clk,d,q);
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(* ivl_synthesis_off *)
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initial
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begin
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// $dumpfile("test.vcd");
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// $dumpvars(0,test);
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clk = 0;
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d = 0;
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# 1;
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clk = 1;
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# 1;
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if (q !== 3'b0)
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begin
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$display("FAILED - Q isn't 0 on first edge");
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$finish;
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end
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d = 1;
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# 1;
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clk = 0;
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# 1;
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if (q !== 3'b0)
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begin
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$display("FAILED - Q isn't 0 after first falling edge");
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$finish;
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end
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# 1;
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clk = 1;
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# 1;
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if (q !== 3'b111)
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begin
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#1 ;
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$display("FAILED - Q isn't 1 2nd raising edge");
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$finish;
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end
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# 1;
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clk = 0;
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# 1;
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if (q !== 3'b111)
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begin
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$display("FAILED - Q isn't 1 after 2nd falling edge");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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