40 lines
599 B
Verilog
40 lines
599 B
Verilog
// Check that non-ANSI output ports that have a SystemVerilog data type are
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// elaborated as variables and be assigned a value.
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typedef struct packed { int x; } T1;
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typedef enum { A } T2;
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typedef T1 [1:0] T3;
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module test1;
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output reg a;
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output reg [1:0] b;
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output integer c;
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output time d;
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output bit e;
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output logic f;
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output shortint g;
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output int h;
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output longint i;
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output real r;
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output T1 x;
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output T2 y;
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output T3 z;
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initial begin
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a = '0;
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b = '0;
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c = '0;
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d = '0;
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e = '0;
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f = '0;
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g = '0;
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h = '0;
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r = 0.0;
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x = '0;
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y = A;
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z = '0;
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$display("PASSED");
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end
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endmodule
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