14 lines
296 B
Verilog
14 lines
296 B
Verilog
// Check that it is an error to declare a non-ANSI module port without implicit
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// packed dimensions if it is later redeclared as a vector typed variable and
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// the vector type is not a scalar.
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module test(x);
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output x;
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reg [7:0] x;
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initial begin
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$display("FAILED");
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end
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endmodule
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