17 lines
338 B
Verilog
17 lines
338 B
Verilog
// Check that it is possible to declare the data type for a vector type module
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// port before the direction for non-ANSI style port declarations.
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module test(x);
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reg [7:0] x;
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output [7:0] x;
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initial begin
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if ($bits(x) == 8) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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