21 lines
406 B
Verilog
21 lines
406 B
Verilog
// Check that it is possible to declare the data type for a packed array module
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// port separately from the direction for non-ANSI style port declarations.
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// declarations.
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typedef logic [3:0] T1;
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typedef T1 [7:0] T2;
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module test(x);
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output x;
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T2 x;
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initial begin
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if ($bits(x) == $bits(T2)) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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