15 lines
352 B
Verilog
15 lines
352 B
Verilog
// Check that it is an error to declare a non-ANSI module port with implicit
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// packed dimensions if it is later redeclared as an atom2 typed variable. Even
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// if the size of the packed dimensions matches that of the size of the atom2
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// type.
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module test(x);
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output [15:0] x;
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shortint x;
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initial begin
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$display("FAILED");
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end
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endmodule
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