38 lines
1.1 KiB
Verilog
38 lines
1.1 KiB
Verilog
//
|
|
// Copyright (c) 1999 Steven Wilson (stevew@home.com)
|
|
//
|
|
// This source code is free software; you can redistribute it
|
|
// and/or modify it in source code form under the terms of the GNU
|
|
// General Public License as published by the Free Software
|
|
// Foundation; either version 2 of the License, or (at your option)
|
|
// any later version.
|
|
//
|
|
// This program is distributed in the hope that it will be useful,
|
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
// GNU General Public License for more details.
|
|
//
|
|
// You should have received a copy of the GNU General Public License
|
|
// along with this program; if not, write to the Free Software
|
|
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
|
//
|
|
// SDW - Validate various module formats
|
|
|
|
|
|
module foo(a);
|
|
output a;
|
|
wire a = 1'b1 ;
|
|
endmodule
|
|
|
|
module main;
|
|
wire b;
|
|
foo foo1 (.a());
|
|
foo foo2 (.a(b));
|
|
|
|
initial
|
|
if(!b)
|
|
$display("FAILED - 3.12B - Module with output only failed");
|
|
else
|
|
$display("PASSED");
|
|
endmodule // main
|