160 lines
3.4 KiB
Verilog
160 lines
3.4 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate parameter passing override in module declaration.
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//
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// Build a single line of storage - Note it's
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//
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module reg32 (clk,we, din, dout);
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parameter WIDTH=32;
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input we;
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input clk;
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input [WIDTH-1:0] din;
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output [WIDTH-1:0] dout;
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reg [WIDTH-1:0] store;
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always @(posedge clk)
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if(we)
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store <= din;
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assign dout = store ;
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endmodule
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module memory(clk, we, addr, din, dout);
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parameter WIDTH=8;
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input clk;
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input we;
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input [1:0] addr;
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input [WIDTH-1:0] din;
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output [WIDTH-1:0] dout;
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reg [WIDTH-1:0] dout;
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wire [WIDTH-1:0] dout0,dout1,dout2,dout3;
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reg we0,we1,we2,we3;
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reg32 #(WIDTH) reg0 (.clk(clk),.we(we0),.din(din[WIDTH-1:0]),
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.dout(dout0[WIDTH-1:0]));
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reg32 #(WIDTH) reg1 (.clk(clk),.we(we1),.din(din[WIDTH-1:0]),
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.dout(dout1[WIDTH-1:0]));
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reg32 #(WIDTH) reg2 (.clk(clk),.we(we2),.din(din[WIDTH-1:0]),
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.dout(dout2[WIDTH-1:0]));
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reg32 #(WIDTH) reg3 (.clk(clk),.we(we3),.din(din[WIDTH-1:0]),
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.dout(dout3[WIDTH-1:0]));
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//
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// Build we decode
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//
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always @(addr or we)
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case (addr)
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2'b00: begin
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we0 = we;
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we1 = 0;
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we2 = 0;
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we3 = 0;
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end
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2'b01: begin
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we0 = 0;
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we1 = we;
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we2 = 0;
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we3 = 0;
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end
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2'b10: begin
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we0 = 0;
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we1 = 0;
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we2 = we;
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we3 = 0;
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end
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2'b11: begin
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we0 = 0;
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we1 = 0;
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we2 = 0;
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we3 = we;
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end
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endcase
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//
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// Connect dout to register output
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//
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always @(addr or dout0 or dout1 or dout2 or dout3)
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case (addr)
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2'b00: dout = dout0;
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2'b01: dout = dout1;
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2'b10: dout = dout2;
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2'b11: dout = dout3;
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endcase
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endmodule
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module top;
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parameter WIDTH=8;
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reg clk;
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reg we;
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reg [1:0] addr;
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reg [WIDTH-1:0] din;
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reg error;
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wire [WIDTH-1:0] dout;
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memory mem (clk, we, addr, din, dout);
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initial
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begin
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// $dumpfile("test.vcd");
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// $dumpvars(0,top.mem.reg0);
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clk = 0;
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error =0;
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#3;
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we = 1;
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addr = 0;
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din = 32'b0_00;
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#10;
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addr = 1;
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din = 32'h1;
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#10;
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addr = 2;
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din = 32'h2;
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#10;
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addr = 3;
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din = 32'h3;
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#10;
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we = 0;
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addr = 0;
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#1;
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if(dout[7:0] !== 8'h00)
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begin
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$display("FAILED - Ram[0] not 0, is %h",dout[7:0]);
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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$finish ;
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end
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always #(5) clk = ~clk;
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endmodule
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