65 lines
1.1 KiB
Verilog
65 lines
1.1 KiB
Verilog
module main;
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reg [7:0] data_i;
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reg [2:0] addr;
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reg clk, rst, wr;
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reg [7:0] data_o, buff[0:7];
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(* ivl_synthesis_on *)
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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data_o <= 8'h0;
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else if (wr) begin
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buff[addr] <= data_i;
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data_o <= data_i;
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end else
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data_o <= buff[addr];
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end
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(* ivl_synthesis_off *)
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initial begin
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clk = 0;
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rst = 1;
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wr = 1;
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addr = 0;
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data_i = 8'hff;
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#1 clk = 1;
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#1 clk = 0;
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if (data_o !== 8'h00) begin
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$display("FAILED -- reset data_o=%b", data_o);
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$finish;
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end
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rst = 0;
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wr = 1;
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for (addr = 0; addr < 7; addr = addr+1) begin
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data_i = addr;
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#1 clk = 1;
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#1 clk = 0;
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if (data_o !== data_i) begin
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$display("FAILED -- write data_i=%h, data_o=%h", data_i, data_o);
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$finish;
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end
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end
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wr = 0;
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data_i = 8'hff;
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for (addr = 0 ; addr < 7; addr = addr+1) begin
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#1 clk = 1;
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#1 clk = 0;
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if (data_o !== {5'b00000, addr}) begin
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$display("FAILED -- read addr=%h, data_o=%h", addr, data_o);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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