63 lines
1.0 KiB
Verilog
63 lines
1.0 KiB
Verilog
module main;
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reg [7:0] mem [7:0], D;
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reg [2:0] radr, wadr;
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reg wr, rst, clk;
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/*
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* This implements the synchronous write port to the memory.
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*/
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always @(posedge clk)
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if (rst) begin
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mem[0] <= 0;
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mem[1] <= 0;
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mem[2] <= 0;
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mem[3] <= 8'h33;
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mem[5] <= 8'h55;
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mem[6] <= 0;
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mem[7] <= 0;
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end else
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if (wr) begin
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mem[wadr] <= D;
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end
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// This is the asynchronous read port from the memory.
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wire[7:0] Q = mem[radr];
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initial begin
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wr = 0;
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rst = 1;
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clk = 0;
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#1 clk = 1;
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#1 clk = 0;
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radr = 3;
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#1 if (Q !== 8'h33) begin
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$display("FAILED -- mem[3] == 'b%b", Q);
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$finish;
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end
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radr = 5;
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#1 if (Q !== 8'h55) begin
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$display("FAILED == mem[5] == 'b%b", Q);
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$finish;
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end
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wadr = 4;
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wr = 1;
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rst = 0;
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D = 'h44;
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#1 clk = 1;
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#1 clk = 0;
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radr = 4;
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#1 if (Q !== 8'h44) begin
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$display("FAILED -- mem[4] == 'b%b", Q);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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