81 lines
1.3 KiB
Verilog
81 lines
1.3 KiB
Verilog
`begin_keywords "1364-2005"
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module main;
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reg [3:0] foo, bar;
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reg [1:0] adr;
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reg bit, rst, clk;
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reg load_enable, write_enable;
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(* ivl_synthesis_on *)
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always @(posedge clk or posedge rst)
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if (rst) begin
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foo <= 0;
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end else if (load_enable) begin
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foo <= bar;
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end else if (write_enable) begin
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foo[adr] <= bit;
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end
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(* ivl_synthesis_off *)
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initial begin
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rst = 1;
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clk = 0;
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bar = 4'bzzzz;
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load_enable = 0;
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write_enable = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (foo !== 4'b0000) begin
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$display("FAILED -- reset foo=%b", foo);
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$finish;
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end
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rst = 0;
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bar = 4'b1001;
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load_enable = 1;
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write_enable = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (foo !== bar) begin
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$display("FAILED -- load foo=%b, bar=%b", foo, bar);
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$finish;
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end
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load_enable = 0;
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write_enable = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (foo !== 4'b1001) begin
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$display("FAILED -- foo=%b after clk", foo);
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$finish;
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end
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adr = 1;
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bit = 1;
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load_enable = 0;
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write_enable = 1;
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#1 clk = 1;
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#1 clk = 0;
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if (foo !== 4'b1011) begin
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$display("FAILED -- foo=%b, adr=%b, bit=%b", foo, adr, bit);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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`end_keywords
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