118 lines
2.3 KiB
Verilog
118 lines
2.3 KiB
Verilog
/***********************************************************************
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Array access test cases
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Copyright (C) 2001 Eric LaForest, ecl@pet.dhs.org
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Licenced under GPL
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***********************************************************************/
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module wire_test_case (array_out, clock, reset);
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output [15:0] array_out;
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input clock, reset;
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reg [3:0] readptr;
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reg [15:0] body [15:0];
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wire [15:0] array_out;
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assign array_out = body[readptr];
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// reg [15:0] array_out;
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// always @(readptr or body[readptr]) begin
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// array_out <= body[readptr];
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// end
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always @(posedge clock) begin
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if (reset == 0) begin
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readptr <= 16'h0000;
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body[0] <= 16'h0001; // Fibonnacci
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body[1] <= 16'h0002;
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body[2] <= 16'h0003;
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body[3] <= 16'h0005;
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body[4] <= 16'h0008;
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body[5] <= 16'h000D;
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body[6] <= 16'h0015;
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end
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else begin
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readptr <= readptr + 16'h0001;
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end
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end
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endmodule
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module always_test_case (array_out, clock, reset);
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output [15:0] array_out;
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input clock, reset;
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reg [3:0] readptr;
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reg [15:0] body [15:0];
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// wire [15:0] array_out;
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// assign array_out = body[readptr];
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reg [15:0] array_out;
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always @(readptr or body[readptr]) begin
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array_out <= body[readptr];
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end
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always @(posedge clock) begin
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if (reset == 0) begin
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readptr <= 16'h0000;
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body[0] <= 16'h0001; // Fibonnacci
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body[1] <= 16'h0002;
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body[2] <= 16'h0003;
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body[3] <= 16'h0005;
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body[4] <= 16'h0008;
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body[5] <= 16'h000D;
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body[6] <= 16'h0015;
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end
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else begin
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readptr <= readptr + 16'h0001;
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end
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end
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endmodule
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module BENCH ();
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wire [15:0] array_out1, array_out2;
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reg clock, reset;
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integer count;
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integer errors;
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wire_test_case usingwire (array_out1, clock, reset);
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always_test_case usingalways (array_out2, clock, reset);
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initial begin
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// $dumpfile("waves.vcd");
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// $dumpvars(0, BENCH);
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clock <= 0;
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reset <= 0;
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count <= 0;
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#1000;
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if (errors == 0)
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$display("PASSED");
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$finish;
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end
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always begin
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# 10 clock <= ~clock;
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end
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always @(posedge clock) begin
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count <= count + 1;
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case (count)
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10: begin
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reset <= 1;
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end
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endcase
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end
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initial errors = 0;
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always @(negedge clock)
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if (array_out1 !== array_out2)
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begin
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$display("FAILED: %b !== %b", array_out1, array_out2);
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errors = errors + 1;
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end
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endmodule
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