108 lines
2.4 KiB
Verilog
108 lines
2.4 KiB
Verilog
// test_mis.v - Testbench for mis.bvrl
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// 01-22-01 E. Brombaugh
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/*
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* Copyright (c) 2001 Eric Brombaugh <ebrombau@intersil.com>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* The mis'' module was generated by the synopsis module compiler
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* and is typical of the modules it generates. The testbench was hand
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* coded. This file was merged into a single file using the Verilog
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* preprocessor.
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*/
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`timescale 1ns / 10 ps
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module mis( y, a, b );
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input [3:0] a;
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input [3:0] b;
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output [12:0] y;
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wire dpa_zero, dpa_one;
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wire [5:0] const__1_24_;
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wire [7:0] C0;
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wire [6:0] const__2_33_;
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wire [7:0] C1;
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wire [12:0] y_1_;
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assign dpa_zero= 1024'h0;
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assign dpa_one= 1024'h1;
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assign const__1_24_=- 1024'h18;
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assign const__2_33_=- 1024'h21;
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/* mis.mcl:4 module mis (y, a, b); */
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/* mis.mcl:5 input signed [3:0] a, b; */
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/* mis.mcl:10 C0 = -24; */
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assign C0= ((const__1_24_[4:0]-(const__1_24_[5]<<5)));
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/* mis.mcl:11 C1 = -33; */
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assign C1= ((const__2_33_[5:0]-(const__2_33_[6]<<6)));
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/* mis.mcl:13 y = C0*a + C1*b; */
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assign y_1_= ((C0[6:0]-(C0[7]<<7))*(a[2:0]-(a[3]<<3))+
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(C1[6:0]-(C1[7]<<7))*(b[2:0]-(b[3]<<3)));
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/* mis.mcl:6 output signed [12:0] y; */
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assign y = y_1_[12:0];
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/* mis.mcl:4 module mis (y, a, b); */
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/* mis.mcl:13 y = C0*a + C1*b; */
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/*User Defined Aliases */
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endmodule
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module test_mis;
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reg [10:0] count;
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reg clk;
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reg [3:0] a, b;
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wire [12:0] y;
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mis u1(y, a, b);
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initial
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begin
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count = 0;
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clk = 0;
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a = 0;
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b = 0;
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end
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always
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#10 clk = ~clk;
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always @(posedge clk)
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begin
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a = count[3:0];
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b = count[7:4];
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#10
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$display("%h %h %h", a, b, y);
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count = count + 1;
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if(count == 0)
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$finish(0);
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end
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endmodule
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