173 lines
4.1 KiB
Verilog
173 lines
4.1 KiB
Verilog
/*
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* Copyright (c) 2001 Stephan Boettcher <stephan@nevis.columbia.edu>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// $Id: many_drivers.v,v 1.2 2001/07/21 02:30:44 stevewilliams Exp $
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// $Log: many_drivers.v,v $
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// Revision 1.2 2001/07/21 02:30:44 stevewilliams
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// Get the expected blended values right.
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//
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// Revision 1.1 2001/07/18 01:22:26 sib4
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// test for nets with many drivers
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//
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module test;
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reg [66:0] in;
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wire out;
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buf (out, in[ 0]);
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buf (out, in[ 1]);
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buf (out, in[ 2]);
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buf (out, in[ 3]);
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buf (out, in[ 4]);
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buf (out, in[ 5]);
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buf (out, in[ 6]);
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buf (out, in[ 7]);
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buf (out, in[ 8]);
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buf (out, in[ 9]);
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buf (out, in[10]);
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buf (out, in[11]);
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buf (out, in[12]);
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buf (out, in[13]);
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buf (out, in[14]);
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buf (out, in[15]);
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buf (out, in[16]);
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buf (out, in[17]);
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buf (out, in[18]);
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buf (out, in[19]);
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buf (out, in[20]);
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buf (out, in[21]);
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buf (out, in[22]);
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buf (out, in[23]);
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buf (out, in[24]);
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buf (out, in[25]);
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buf (out, in[26]);
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buf (out, in[27]);
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buf (out, in[28]);
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buf (out, in[29]);
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buf (out, in[30]);
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buf (out, in[31]);
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buf (out, in[32]);
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buf (out, in[33]);
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buf (out, in[34]);
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buf (out, in[35]);
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buf (out, in[36]);
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buf (out, in[37]);
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buf (out, in[38]);
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buf (out, in[39]);
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buf (out, in[40]);
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buf (out, in[41]);
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buf (out, in[42]);
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buf (out, in[43]);
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buf (out, in[44]);
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buf (out, in[45]);
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buf (out, in[46]);
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buf (out, in[47]);
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buf (out, in[48]);
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buf (out, in[49]);
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buf (out, in[50]);
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buf (out, in[51]);
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buf (out, in[52]);
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buf (out, in[53]);
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buf (out, in[54]);
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buf (out, in[55]);
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buf (out, in[56]);
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buf (out, in[57]);
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buf (out, in[58]);
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buf (out, in[59]);
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buf (out, in[60]);
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buf (out, in[61]);
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buf (out, in[62]);
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buf (out, in[63]);
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buf (out, in[64]);
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buf (out, in[65]);
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buf (out, in[66]);
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reg err;
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// Verilog-XL yields out=x for all but the first two
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initial
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begin
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err = 0;
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in = 67'b0;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'b0) err = 1;
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in = ~67'b0;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'b1) err = 1;
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in = 67'bz;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = 67'bx;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = 67'h 5_55555555_55555555;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = ~67'h 5_55555555_55555555;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = 67'h 0_xxxxxxxx_00000000;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = ~67'h 0_xxxxxxxx_00000000;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = 67'h x_xxxxxxxx_00000000;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = ~67'h x_xxxxxxxx_00000000;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = 67'h x_55555555_55555555;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = ~67'h x_55555555_55555555;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = 67'h 1_ffffxxxx_00000000;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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in = ~67'h 1_ffffxxxx_00000000;
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#1 $display("in=%b out=%b", in, out);
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if (out!==1'bx) err = 1;
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if (err)
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$display("FAILED");
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else
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$display("PASSED");
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$finish;
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end
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endmodule
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