25 lines
591 B
Verilog
25 lines
591 B
Verilog
module test();
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reg [31:0] a, b;
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reg [65:0] a_l, b_l;
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wire [31:0] result = a / b;
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wire [31:0] mod = a % b;
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wire [65:0] result_l = a_l / b_l;
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wire [65:0] mod_l = a_l % b_l;
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initial begin
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a = 'h1;
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b = 'h1;
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a_l = 'h1;
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b_l = 'h1;
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#1; // Need some delay for the calculations to run.
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// b_l = 'h0; // This will now fail with an error.
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$display("Using normal math routines.");
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$display("Result: %0d\nModulus: %h", result, mod);
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$display("\nUsing wide math routines.");
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$display("Result: %0d\nModulus: %h", result_l, mod_l);
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end
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endmodule
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