148 lines
2.2 KiB
Verilog
148 lines
2.2 KiB
Verilog
module test;
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// The SystemVerilog standard requires that the right side of a logical operator
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// is not evaluated under certain conditions.
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// For && if the left hand side is false the right hand side is not evalualted
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// For || if the left hand side is true the right hand side is not evalualted
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wire a0 = 1'b0;
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wire a1 = 1'b1;
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wire ax = 1'bx;
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wire az = 1'bz;
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integer b;
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logic [1:0] c;
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bit failed = 1'b0;
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initial begin
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// AND with first parameter 1'b0
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b = 0;
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c = 2'b00;
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if (a0 && b++ && ++b)
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c = 2'b01;
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failed |= b !== 0;
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failed |= c !== 2'b00;
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c = a0 && b++ && ++b;
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failed |= b !== 0;
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failed |= c !== 2'b00;
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// AND with first parameter 1'b1
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b = 0;
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c = 2'b00;
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if (a1 && b++ && ++b)
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c = 2'b01;
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failed |= b !== 1;
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failed |= c !== 2'b00;
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c = a1 && b++ && ++b;
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failed |= b !== 3;
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failed |= c !== 2'b01;
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// AND with first parameter 1'bz
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b = 0;
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c = 2'b00;
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if (az && b++ && ++b)
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c = 2'b01;
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failed |= b !== 1;
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failed |= c !== 2'b00;
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c = az && b++ && ++b;
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failed |= b !== 3;
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failed |= c !== 2'b0x;
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// AND with first parameter 1'bz
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b = 0;
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c = 0;
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if (ax && b++ && ++b)
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c = 2'b01;
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failed |= b !== 1;
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failed |= c !== 2'b00;
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c = ax && b++ && ++b;
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failed |= b !== 3;
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failed |= c !== 2'b0x;
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// OR with first parameter 1'b0
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b = 0;
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c = 0;
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if (a0 || b++ || ++b)
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c = 2'b01;
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failed |= b !== 2;
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failed |= c !== 2'b01;
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c = a0 || b++ || ++b;
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failed |= b !== 3;
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failed |= c !== 2'b01;
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// OR with first parameter 1'b1
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b = 0;
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c = 2'b00;
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if (a1 || b++ || ++b)
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c = 2'b01;
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failed |= b !== 0;
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failed |= c !== 2'b01;
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c = a1 || b++ || ++b;
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failed |= b !== 0;
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failed |= c !== 2'b01;
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// OR with first parameter 1'bz
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b = 0;
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c = 2'b00;
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if (az || b++ || ++b)
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c = 2'b01;
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failed |= b !== 2;
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failed |= c !== 2'b01;
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b = 0;
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c = az || b++;
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failed |= b !== 1;
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failed |= c !== 2'b0x;
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// OR with first parameter 1'bz
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b = 0;
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c = 0;
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if (ax || b++ || ++b)
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c = 2'b01;
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failed |= b !== 2;
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failed |= c !== 2'b01;
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b = 0;
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c = ax || b++;
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failed |= b !== 1;
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failed |= c !== 2'b0x;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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