48 lines
1.3 KiB
Verilog
48 lines
1.3 KiB
Verilog
/*
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* Copyright (c) 2001 Stephan Boettcher <stephan@nevis.columbia.edu>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// $Id: ldelay5.v,v 1.1 2001/12/26 23:45:57 sib4 Exp $
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// Test for delays in structural logic. Multiple UDP instances.
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module test;
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wire [1:2] q, a, b;
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drec U1(q[1], a[1], b[1]);
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drec U2(q[2], a[2], b[2]);
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initial $display("PASSED");
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endmodule
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module drec (q, a, b);
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output q;
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input a, b;
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U_drec #1 U(q, a, b);
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endmodule
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primitive U_drec (q, a, b);
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output q;
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input a, b;
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table
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1 0 : 1 ;
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0 1 : 0 ;
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endtable
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endprimitive
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