67 lines
1.5 KiB
Verilog
67 lines
1.5 KiB
Verilog
/*
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* Copyright (c) 2001 Stephan Boettcher <stephan@nevis.columbia.edu>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// $Id: ldelay1.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $
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// Test for delays in structural logic. Inertial delays
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module test;
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wire q;
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reg a, b;
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and #6 (q, a, b);
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task ok;
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input qq;
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reg error;
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begin
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if (q !== qq)
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begin
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error = 1;
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$display("%0d: FAILED: q=%b, expect %b", $time, q, qq);
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end
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end
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endtask
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initial
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begin
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ok.error = 0;
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// $dumpvars;
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a <= 0;
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b <= 1;
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#5 ok(1'b x);
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#2 ok(1'b 0);
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a <= 1;
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#5 ok(1'b 0);
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#2 ok(1'b 1);
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a <= 0;
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#3 ok(1'b 1);
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a <= 1;
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#1 ok(1'b 1);
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#1 ok(1'b 1);
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#1 ok(1'b 1);
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#1 ok(1'b 1);
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#1 ok(1'b 1);
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#1 ok(1'b 1);
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#1 ok(1'b 1);
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if (!ok.error)
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$display("PASSED");
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end
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endmodule
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