48 lines
720 B
Verilog
48 lines
720 B
Verilog
module main;
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reg q0, q1, clk, clr;
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(* ivl_synthesis_on *)
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always @(posedge clk, posedge clr)
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if (clr) begin
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//q0 <= 0;
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//q1 <= 0;
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{q0, q1} <= 2'b00;
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end else begin
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{q1, q0} <= {q1, q0} + 1;
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end
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(* ivl_synthesis_off *)
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initial begin
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clk = 0;
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clr = 1;
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#1 clk = 1;
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#1 clk = 0;
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if ({q1,q0} !== 2'b00) begin
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$display("FAILED");
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$finish;
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end
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clr = 0;
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#1 clk = 1;
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#1 clk = 0;
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if ({q1,q0} !== 2'b01) begin
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$display("FAILED");
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if ({q1,q0} !== 2'b10) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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