157 lines
3.9 KiB
Verilog
157 lines
3.9 KiB
Verilog
module top;
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real rval1, rval2;
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reg val1, val2;
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reg [3:0] wval1, wval2;
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reg [1:0] wres;
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reg res;
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reg pass;
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initial begin
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pass = 1'b1;
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val1 = 1'b0;
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val2 = 1'b0;
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res = val1 <-> val2;
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if (res !== 1'b1) begin
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$display("FAILED: 1'b0 <-> 1'b0 returned %b not 1'b1", res);
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pass = 1'b0;
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end
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val2 = 1'b1;
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res = val1 <-> val2;
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if (res !== 1'b0) begin
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$display("FAILED: 1'b0 <-> 1'b1 returned %b not 1'b0", res);
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pass = 1'b0;
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end
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val2 = 1'bx;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'b0 <-> 1'bx returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val2 = 1'bz;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'b0 <-> 1'bz returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val1 = 1'b1;
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val2 = 1'b0;
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res = val1 <-> val2;
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if (res !== 1'b0) begin
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$display("FAILED: 1'b1 <-> 1'b0 returned %b not 1'b0", res);
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pass = 1'b0;
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end
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val2 = 1'b1;
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res = val1 <-> val2;
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if (res !== 1'b1) begin
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$display("FAILED: 1'b1 <-> 1'b1 returned %b not 1'b1", res);
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pass = 1'b0;
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end
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val2 = 1'bx;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'b1 <-> 1'bx returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val2 = 1'bz;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'b1 <-> 1'bz returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val1 = 1'bx;
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val2 = 1'b0;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val2 = 1'b1;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'bx <-> 1'b1 returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val2 = 1'bx;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'bx <-> 1'bx returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val2 = 1'bz;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'bx <-> 1'bz returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val1 = 1'bz;
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val2 = 1'b0;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'bz <-> 1'b0 returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val2 = 1'b1;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'bz <-> 1'b1 returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val2 = 1'bx;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'bz <-> 1'bx returned %b not 1'bx", res);
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pass = 1'b0;
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end
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val2 = 1'bz;
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res = val1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 1'bz <-> 1'bz returned %b not 1'bx", res);
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pass = 1'b0;
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end
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rval1 = 0.0;
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val2 = 1'b0;
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res = rval1 <-> val2;
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if (res !== 1'b1) begin
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$display("FAILED: 0.0 <-> 1'b0 returned %b not 1'b1", res);
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pass = 1'b0;
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end
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val1 = 1'b0;
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rval2 = 2.0;
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res = val1 <-> rval2;
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if (res !== 1'b0) begin
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$display("FAILED: 1'b0 <-> 2.0 returned %b not 1'b0", res);
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pass = 1'b0;
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end
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rval1 = 2.0;
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val2 = 1'bx;
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res = rval1 <-> val2;
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if (res !== 1'bx) begin
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$display("FAILED: 2.0 <-> 1'bx returned %b not 1'bx", res);
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pass = 1'b0;
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end
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rval1 = -5.0;
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rval2 = 2.0;
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res = rval1 <-> rval2;
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if (res !== 1'b1) begin
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$display("FAILED: -5.0 <-> -2.0 returned %b not 1'b1", res);
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pass = 1'b0;
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end
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wval1 = 4'b0110;
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wval2 = 4'b1001;
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wres = wval1 <-> wval2;
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if (wres !== 2'b01) begin
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$display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b01", wres);
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pass = 1'b0;
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end
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wres = $signed(wval1 <-> wval2);
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if (wres !== 2'b11) begin
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$display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b11", wres);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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