95 lines
2.6 KiB
Verilog
95 lines
2.6 KiB
Verilog
// Three basic tests in here:
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// 1. byte must be initialised before any initial or always block
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// 2. assignments to (unsigned) bytes with random numbers
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// 3. assignments to (unsigned) bytes with random values including X and Z
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module ibyte_test;
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parameter TRIALS = 100;
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parameter MAX = 'h7fff;
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reg [15:0] ar; // should it be "reg unsigned [7:0] aw"?
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reg [15:0] ar_xz; // same as above here?
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reg [15:0] ar_expected; // and here
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shortint unsigned bu;
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shortint unsigned bu_xz;
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integer i;
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assign bu = ar;
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assign bu_xz = ar_xz;
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// all test
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initial begin
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// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
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if (bu !== 16'b0 | bu_xz != 16'b0)
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begin
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$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
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$finish;
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end
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// random numbers
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for (i = 0; i< TRIALS; i = i+1)
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begin
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#1;
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ar = {$random} % MAX;
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#1;
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if (bu !== ar)
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begin
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$display ("FAILED - incorrect assigment to byte: %b", bu);
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$finish;
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end
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end
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# 1;
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// with 'x injections (Section 4.3.2 of IEEE 1850 LRM)
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for (i = 0; i< TRIALS; i = i+1)
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begin
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#1;
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ar = {$random} % MAX;
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ar_xz = xz_inject (ar);
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ar_expected = xz_expected (ar_xz);
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#1;
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if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0
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begin
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$display ("FAILED - incorrect assigment to byte (when 'x): %b", bu);
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$finish;
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end
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end
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# 1;
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$display("PASSED");
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end
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// this returns X and Z states into bit random positions for a value
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function [7:0] xz_inject (input [7:0] value); // should it be "input unsigned [7:0]" instead?
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integer i, temp;
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begin
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temp = {$random} % MAX;
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for (i=0; i<16; i=i+1)
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begin
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if (temp[i] == 1'b1)
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begin
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temp = $random % MAX;
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if (temp <= 0)
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value[i] = 1'bx; // 'x noise
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else
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value[i] = 1'bz; // 'z noise
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end
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end
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xz_inject = value;
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end
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endfunction
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// this function returns bit positions with either X or Z to 0 for an input value
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function [15:0] xz_expected (input [15:0] value_xz); // should it be "input unsigned [7:0] instead?
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integer i;
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begin
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for (i=0; i<16; i=i+1)
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begin
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if (value_xz[i] === 1'bx || value_xz[i] === 1'bz )
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value_xz[i] = 1'b0; // forced to zero
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end
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xz_expected = value_xz;
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end
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endfunction
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endmodule
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