52 lines
1.4 KiB
Verilog
52 lines
1.4 KiB
Verilog
/*
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* integer4ge - a verilog test for integer greater-or-equal conditional >=
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*
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* Copyright (C) 2000 Steve Wilson stevew@home.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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* Boston, MA 02111-1307 USA
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*/
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`timescale 100s/1s
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module test;
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reg [3:0] result;
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reg error;
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integer num1;
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wire [3:0] result1;
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assign result1 = 1 + (num1 /4);
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initial
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begin
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error = 0;
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num1 = 32'h24 ;
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result = 1 + (num1 / 4);
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#1;
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if(result !== 4'ha)
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begin
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$display("FAILED - division didn't work s/b A, is %h",result);
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error = 1;
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end
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if(result1 !== 4'ha)
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begin
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$display("FAILED - assign division didn't work s/b A, is %h",result1);
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule
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