69 lines
1.6 KiB
Verilog
69 lines
1.6 KiB
Verilog
/*
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* integer1 - a verilog test for integer conditionals
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*
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* Copyright (C) 1999 Stephen G. Tell
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* Portions inspired by qmark.v by Steven Wilson (stevew@home.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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* Boston, MA 02111-1307 USA
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*/
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module integer1lt;
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integer a;
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integer b;
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reg error;
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initial begin
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error = 0;
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a = 2;
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if(a < 2) begin
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$display("FAILED 2 < 2");
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error = 1;
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end
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a = 3;
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if(a < 2) begin
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$display("FAILED 3 < 2");
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error = 1;
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end
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a = 1;
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if(a < 2) begin
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b = 1;
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end else begin
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$display("FAILED 1 < 2");
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error = 1;
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end
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b = 0;
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for(a = 0; a < 5; a = a + 1) begin
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b = b + a;
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end // for (a = 0; a < 5; a = a + 1)
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if(b != 10) begin
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$display("FAILED forloop b=%d expected 10", b);
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule
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