20 lines
558 B
Verilog
20 lines
558 B
Verilog
module top;
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reg [47:0] out1, out2, out3, out4, out5;
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integer i;
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initial begin
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for (i=-1 ; i<2; i=i+1) begin
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// i is signed so should it be sign extended?
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out1 = 48'd16 + i;
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// I would have expected this to be the same as (i+0) below!
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out2 = 48'd16 + (i);
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// All the rest of these are sign extended?
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out3 = 48'd16 + (i+0);
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out4 = 48'sd16 + i;
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out5 = 48'd16 + (i-1);
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$display("16 + %2d = %10d, %10d, %2d, %2d, -1 = %2d",
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i, out1, out2, out3, out4, out5);
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end
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end
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endmodule
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