117 lines
3.3 KiB
Verilog
117 lines
3.3 KiB
Verilog
/*
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* Copyright (c) 2000 Yasuhisa Kato <ykato@mac.com>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// Modified my stevew@home.com to be self-checking per the comments.
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module main;
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reg clk ;
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initial begin clk = 0 ; forever #5 clk = ~clk ; end
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initial #20 $finish;
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wire w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o ;
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reg r, rw ;
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reg error;
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// z <- (z) = z
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assign ww = w ; // z <- (z) = z
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assign wr = r ; // x <- (z) = x
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assign w1 = 'b1 ; // 1 <- (z) = 1
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assign wwr = w & r ; // x <- z & x
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assign ww1 = w & 'b1 ; // x <- z & 1
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assign wr1 = r & 'b1 ; // x <- x & 1
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assign wwro= w | r ; // x <- z | x
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assign ww1o= w | 'b1 ; // 1 <- z | 1
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assign wr1o= r | 'b1 ; // 1 <- x | 1
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always @(posedge clk)
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rw <= w ; // x <- (x) = z
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always @(posedge clk)
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begin
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#1;
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$display("%b %b %b %b %b %b %b : %b %b %b : %b %b",
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w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o, r, rw );
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end
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initial
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begin
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error = 0;
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#19;
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if(ww !== 1'bz) begin
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error = 1;
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$display("FAILED - ww s/b z, is %h",ww);
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end
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if(wr !== 1'bx) begin
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error = 1;
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$display("FAILED - wr s/b x, is %h",wr);
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end
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if(w1 !== 1'b1) begin
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error = 1;
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$display("FAILED - wr s/b 1, is %h",wr);
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end
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if(wwr !== 1'bx) begin
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error = 1;
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$display("FAILED - wwr s/b x, is %h",wwr);
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end
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if(ww1 !== 1'bx) begin
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error = 1;
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$display("FAILED - ww1 s/b x, is %h",ww1);
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end
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if(wr1 !== 1'bx) begin
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error = 1;
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$display("FAILED - wr1 s/b x, is %h",wr1);
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end
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if(wwro !== 1'bx) begin
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error = 1;
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$display("FAILED - wwro s/b 1, is %h",wwro);
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end
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if(wr1o !== 1'b1) begin
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error = 1;
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$display("FAILED - wr1o s/b 1, is %h",wr1o);
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end
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if(r !== 1'bx) begin
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error = 1;
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$display("FAILED - r s/b x, is %h",r);
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end
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if(r !== 1'bx) begin
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error = 1;
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$display("FAILED - r s/b x, is %h",r);
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end
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if(rw !== 1'bz) begin
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error = 1;
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$display("FAILED - rw s/b z, is %h",r);
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end
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if(error === 0)
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$display("PASSED");
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$finish(0);
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end
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endmodule
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// *Initial Value Test*
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// expected output - This according to XL
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// z z x 1 x x x : x 1 1 : x x
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// z z x 1 x x x : x 1 1 : x z
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// ivl current result
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// z z x 1 x z x : x 1 1 : x x
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// z z x 1 x z x : x 1 1 : x z
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