26 lines
373 B
Verilog
26 lines
373 B
Verilog
module main;
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int foo;
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initial begin
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foo = 1;
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foo ++;
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++ foo;
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if (foo !== 3) begin
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$display("FAILED -- foo=%0d", foo);
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$finish;
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end
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foo --;
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-- foo;
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if (foo !== 1) begin
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$display("FAILED -- foo=%0d", foo);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // main
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