131 lines
6.4 KiB
Verilog
131 lines
6.4 KiB
Verilog
// Test implicit casts during procedural non-blocking assignments.
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module implicit_cast();
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real src_r;
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bit unsigned [7:0] src_u2;
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bit signed [7:0] src_s2;
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logic unsigned [7:0] src_u4;
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logic signed [7:0] src_s4;
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logic unsigned [7:0] src_ux;
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logic signed [7:0] src_sx;
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real dst_r;
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bit unsigned [3:0] dst_u2s;
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bit signed [3:0] dst_s2s;
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bit unsigned [11:0] dst_u2l;
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bit signed [11:0] dst_s2l;
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logic unsigned [3:0] dst_u4s;
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logic signed [3:0] dst_s4s;
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logic unsigned [11:0] dst_u4l;
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logic signed [11:0] dst_s4l;
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bit failed;
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initial begin
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failed = 0;
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src_r = -7;
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src_u2 = 7;
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src_s2 = -7;
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src_u4 = 7;
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src_s4 = -7;
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src_ux = 8'bx0z00111;
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src_sx = 8'bx0z00111;
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$display("cast to real");
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dst_r <= src_r; #1 $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
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dst_r <= src_u2; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
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dst_r <= src_s2; #1 $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
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dst_r <= src_u4; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
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dst_r <= src_s4; #1 $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
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dst_r <= src_ux; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
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dst_r <= src_sx; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
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$display("cast to small unsigned bit");
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dst_u2s <= src_r; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
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dst_u2s <= src_u2; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
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dst_u2s <= src_s2; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
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dst_u2s <= src_u4; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
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dst_u2s <= src_s4; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
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dst_u2s <= src_ux; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
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dst_u2s <= src_sx; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
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$display("cast to small signed bit");
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dst_s2s <= src_r; #1 $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
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dst_s2s <= src_u2; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
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dst_s2s <= src_s2; #1 $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
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dst_s2s <= src_u4; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
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dst_s2s <= src_s4; #1 $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
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dst_s2s <= src_ux; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
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dst_s2s <= src_sx; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
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$display("cast to large unsigned bit");
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dst_u2l <= src_r; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
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dst_u2l <= src_u2; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
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dst_u2l <= src_s2; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
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dst_u2l <= src_u4; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
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dst_u2l <= src_s4; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
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dst_u2l <= src_ux; #1 $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
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dst_u2l <= src_sx; #1 $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
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$display("cast to large signed bit");
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dst_s2l <= src_r; #1 $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
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dst_s2l <= src_u2; #1 $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
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dst_s2l <= src_s2; #1 $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
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dst_s2l <= src_u4; #1 $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
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dst_s2l <= src_s4; #1 $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
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dst_s2l <= src_ux; #1 $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
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dst_s2l <= src_sx; #1 $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
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$display("cast to small unsigned logic");
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dst_u4s <= src_r; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
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dst_u4s <= src_u2; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
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dst_u4s <= src_s2; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
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dst_u4s <= src_u4; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
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dst_u4s <= src_s4; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
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dst_u4s <= src_ux; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
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dst_u4s <= src_sx; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
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$display("cast to small signed logic");
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dst_s4s <= src_r; #1 $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
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dst_s4s <= src_u2; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
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dst_s4s <= src_s2; #1 $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
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dst_s4s <= src_u4; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
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dst_s4s <= src_s4; #1 $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
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dst_s4s <= src_ux; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
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dst_s4s <= src_sx; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
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$display("cast to large unsigned logic");
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dst_u4l <= src_r; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
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dst_u4l <= src_u2; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
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dst_u4l <= src_s2; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
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dst_u4l <= src_u4; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
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dst_u4l <= src_s4; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
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dst_u4l <= src_ux; #1 $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1;
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dst_u4l <= src_sx; #1 $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1;
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$display("cast to large signed logic");
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dst_s4l <= src_r; #1 $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
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dst_s4l <= src_u2; #1 $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
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dst_s4l <= src_s2; #1 $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
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dst_s4l <= src_u4; #1 $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
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dst_s4l <= src_s4; #1 $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
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dst_s4l <= src_ux; #1 $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1;
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dst_s4l <= src_sx; #1 $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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