33 lines
739 B
Verilog
33 lines
739 B
Verilog
// test that .* implicit ports work with override
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module m(input a, output b, output c, output d, output e);
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assign b = a;
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assign c = ~a;
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assign d = ~a;
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assign e = ~a;
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endmodule
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module top;
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reg a;
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reg x;
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wire b, d;
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m foo(.a(x), .e(), .*, .c(d), .d());
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m foo2(.a(x), .d(), .*, .c(), .e());
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m foo3(.a(x), .*, .d(), .c(), .e());
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m foo4(.*, .a(x), .d(), .c(), .e());
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m foo5(.a(x), .d(), .c(), .*, .e());
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m foo6(.a(x), .d(), .c(), .e(), .*);
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initial begin
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a = 0;
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x = 1;
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#1 if (b !== x || d !== ~x) begin
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$display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d);
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end
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#1 a = 1;
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#1 if (b !== x || d !== ~x) begin
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$display("FAILED -- a=%b, x=%b, b=%b, d=%b", a, x, b, d);
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end
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$display("PASSED");
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end
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endmodule
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