98 lines
1.9 KiB
Verilog
98 lines
1.9 KiB
Verilog
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module test
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(output reg [1:0] foo,
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input wire [1:0] addr,
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input wire in0, in1,
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input wire en0, en1
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/* */);
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localparam foo_default = 2'b00;
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always @*
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begin
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foo = foo_default;
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case (addr)
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0: if (en0) foo[0] = in0;
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1: if (en1) foo[1] = in1;
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2: foo = {in1, in0};
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default: foo = 0;
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endcase
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end
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endmodule // test
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module main;
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wire [1:0] foo;
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reg [1:0] addr;
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reg in0, in1;
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reg en0, en1;
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test dut(.foo(foo), .addr(addr), .in0(in0), .in1(in1), .en0(en0), .en1(en1));
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initial begin
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in0 = 1;
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in1 = 1;
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en0 = 1;
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en1 = 1;
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addr = 3;
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#1 if (foo !== 2'b00) begin
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$display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
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foo, in1, in0, en1, en0, addr);
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$finish;
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end
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addr = 0;
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#1 if (foo !== 2'b01) begin
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$display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
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$finish;
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end
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addr = 1;
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#1 if (foo !== 2'b10) begin
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$display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
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$finish;
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end
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addr = 2;
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#1 if (foo !== 2'b11) begin
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$display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
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$finish;
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end
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en0 = 0;
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en1 = 0;
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addr = 3;
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#1 if (foo !== 2'b00) begin
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$display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
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foo, in1, in0, en1, en0, addr);
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$finish;
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end
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addr = 0;
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#1 if (foo !== 2'b00) begin
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$display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
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foo, in1, in0, en1, en0, addr);
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$finish;
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end
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addr = 1;
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#1 if (foo !== 2'b00) begin
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$display("FAILED -- foo=%b, in=%b%b, addr=%b", foo, in1, in0, addr);
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$finish;
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end
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addr = 2;
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#1 if (foo !== 2'b11) begin
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$display("FAILED -- foo=%b, in=%b%b, en=%b%b, addr=%b",
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foo, in1, in0, en1, en0, addr);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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