67 lines
1.2 KiB
Verilog
67 lines
1.2 KiB
Verilog
module main;
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wire [2:0] value1, value2, value3, value4;
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dut #( .select(1) ) dut1(value1);
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dut #( .select(2) ) dut2(value2);
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dut #( .select(3) ) dut3(value3);
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dut #( .select(4) ) dut4(value4);
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initial begin
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#1 $display("value1=%d, value2=%d, value3=%d, value4=%d",
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value1, value2, value3, value4);
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if (value1 !== 1) begin
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$display("FAILED -- value1=%b", value1);
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$finish;
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end
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if (value2 !== 2) begin
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$display("FAILED -- value2=%b", value2);
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$finish;
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end
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if (value3 !== 3) begin
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$display("FAILED -- value3=%b", value3);
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$finish;
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end
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if (value4 !== 7) begin
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$display("FAILED -- value4=%b", value4);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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module dut(output wire [2:0] value);
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parameter select = 0;
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case (select)
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0: begin
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function [2:0] funfun;
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input integer in;
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funfun = in;
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endfunction // funfun
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assign value = funfun(select);
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end
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1: begin
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function [2:0] funfun;
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input integer in;
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funfun = in;
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endfunction // funfun
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assign value = funfun(1);
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end
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2: assign value = 2;
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3: assign value = 3;
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default:
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assign value = 7;
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endcase // case endcase
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endmodule // dut
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