22 lines
454 B
Verilog
22 lines
454 B
Verilog
// Test behaviour when a multi-bit expression is used as the input of
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// a singleton array of a primitive gate. The standard is explicit
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// that this should be treated as an error.
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module top;
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reg [1:0] in;
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wire [2:0] out;
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buf buf1[0:0](out[0], 1);
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buf buf2[0:0](out[1], 2'b01);
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buf buf3[0:0](out[2], in[1:0]);
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initial begin
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in = 1;
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#1 $display("out = %b", out);
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// this should have failed at compile time
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$display("FAILED");
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end
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endmodule
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