65 lines
1.6 KiB
Verilog
65 lines
1.6 KiB
Verilog
//
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// Copyright (c) 2004 Stephen Williams <steve@icarus.com>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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module main;
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reg C;
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reg [1:0] in;
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wire [1:0] out;
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DFF u [1:0] (out, in, C);
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initial begin
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C <= 0;
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in <= 2'b00;
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#10 C <= 1;
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#10 if (out !== 2'b00) begin
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$display("FAILED -- out=%b, in=%b", out, in);
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$finish;
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end
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C <= 0;
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in <= 2'b10;
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#10 C <= 1;
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#10 if (out !== 2'b10) begin
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$display("FAILED -- out=%b, in=%b", out, in);
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$finish;
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end
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C <= 0;
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in <= 2'b01;
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#10 C <= 1;
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#10 if (out !== 2'b01) begin
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$display("FAILED -- out=%b, in=%b", out, in);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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module DFF(output reg Q, input D, input C);
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always @(posedge C)
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Q <= D;
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endmodule // DFF
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