65 lines
1.8 KiB
Verilog
65 lines
1.8 KiB
Verilog
/*
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* Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This program checks that a function execution that includes part
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* selects properly evaluates expressions. This is inspired by PR#95.
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*/
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module main;
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wire [3:0] a = 4'h1;
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wire [3:0] b = 4'h3;
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reg [1:0] got1, got2;
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reg [7:0] line;
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initial
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begin
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line = 8'h30;
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#1; // Need some delay for the assignments to run.
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got1 = { (b[3:0] == line[7:4]), (a[3:0] == line[3:0]) };
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got2 = test(a, b, line);
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$display("a=%b, b=%b, line=%b, got1=%b, got2=%b",
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a, b, line, got1, got2);
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if (got1 !== 2'b10) begin
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$display("FAILED -- got1 is wrong: %b !== 2'b10", got1);
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$finish;
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end
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if (got1 !== got2) begin
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$display("FAILED -- got2 is incorrect: %b !== %b", got1, got2);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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function [1:0] test;
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input [3:0] a, b;
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input [7:0] line;
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test = { (b == line[7:4]), (a[3:0] == line[3:0]) };
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endfunction // test
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endmodule // main
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