67 lines
1.8 KiB
Verilog
67 lines
1.8 KiB
Verilog
//
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// Copyright (c) 1999 Peter Monta (pmonta@imedia.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// 9/7/99 - SDW - Modified by instantiating Peter's module into a
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// self-checking structure. Moved bar=result inside
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// begin clause in function.
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//
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// SDW - Validate function contains a register
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module main ();
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reg [1:0] val1;
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reg val2;
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reg error;
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function bar;
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input [1:0] arg;
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reg result;
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begin
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result = |arg;
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bar = result;
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end
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endfunction
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initial
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begin
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error = 0;
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val2 = bar(2'b01);
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if(val2 != 1)
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begin
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$display("FAILED function 3.11F - register within a function(1)");
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error = 1;
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end
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val1 = 2'b11 ;
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val2 = bar(val1) ;
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if(val2 != 1)
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begin
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$display("FAILED function 3.11F - register within a function(2)");
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error = 1;
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end
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val2 = bar(2'b00);
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if(val2 != 0)
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begin
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$display("FAILED function 3.11F - register within a function(2)");
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule // main
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