59 lines
1.6 KiB
Verilog
59 lines
1.6 KiB
Verilog
//
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// Copyright (c) 2002 Stephen Williams (steve at icarus.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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module main;
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reg [3:0] val_drv = 4'b0101;
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wire [3:0] val = val_drv;
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initial begin
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#50 if (val !== val_drv) begin
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$display("FAILED -- initial val %b !== %b", val, val_drv);
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$finish;
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end
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force val = 4'b1010;
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#1 if (val !== 4'b1010) begin
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$display("FAILED -- force 1010 failed, val=%b", val);
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$finish;
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end
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// Use force to "lift" the driver.
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force val = 4'bzzzz;
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if (val !== 4'bzzzz) begin
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$display("FAILED -- force z failed, val=%b", val);
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$finish;
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end
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release val;
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#1 if (val !== 4'b0101) begin
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$display("FAILED -- unforced val = %b", val);
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$finish;
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end
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val_drv = 4'b1010;
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#1 if (val !== 4'b1010) begin
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$display("FAILED -- val_drv=%b, val=%b", val_drv, val);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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