76 lines
2.3 KiB
Verilog
76 lines
2.3 KiB
Verilog
/* Copyright (C) 2000 Stephen G. Tell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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* Boston, MA 02111-1307 USA
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*/
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// SDW - reworked a bit to account for the fact that it HAS to be
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/* fopen1 - test $fopen system task */
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module fopen1;
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reg [31:0] fp;
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reg error ;
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initial begin
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fp = $fopen("work/fopen1.out");
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case(fp)
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32'h0000_0001: error = 1;
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32'h0000_0002: error = 0;
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32'h0000_0004: error = 1;
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32'h0000_0008: error = 1;
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32'h0000_0010: error = 1;
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32'h0000_0020: error = 1;
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32'h0000_0040: error = 1;
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32'h0000_0080: error = 1;
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32'h0000_0100: error = 1;
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32'h0000_0200: error = 1;
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32'h0000_0400: error = 1;
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32'h0000_0800: error = 1;
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32'h0000_1000: error = 1;
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32'h0000_2000: error = 1;
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32'h0000_4000: error = 1;
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32'h0000_8000: error = 1;
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32'h0001_0000: error = 1;
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32'h0002_0000: error = 1;
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32'h0004_0000: error = 1;
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32'h0008_0000: error = 1;
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32'h0010_0000: error = 1;
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32'h0020_0000: error = 1;
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32'h0040_0000: error = 1;
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32'h0080_0000: error = 1;
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32'h0100_0000: error = 1;
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32'h0200_0000: error = 1;
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32'h0400_0000: error = 1;
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32'h0800_0000: error = 1;
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32'h1000_0000: error = 1;
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32'h2000_0000: error = 1;
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32'h4000_0000: error = 1;
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32'h8000_0000: error = 1;
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default: error = 1; // std_io!
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endcase
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$display("fp = %b",fp);
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if(error == 0)
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$display("PASSED");
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else
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$display("FAILED");
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$fclose(fp);
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$finish;
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end
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endmodule
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