72 lines
1.2 KiB
Verilog
72 lines
1.2 KiB
Verilog
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module test
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(input wire clk,
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output reg foo, bar,
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input wire foo_valid, foo_in,
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input wire bar_valid, bar_in
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/* */);
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always @(posedge clk)
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begin
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if (foo_valid) foo <= foo_in;
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if (bar_valid) bar <= bar_in;
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end
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endmodule // test
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module main;
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reg clk;
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wire foo, bar;
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reg foo_valid, foo_in;
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reg bar_valid, bar_in;
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test dut (.clk(clk),
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.foo(foo), .bar(bar),
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.foo_valid(foo_valid), .bar_valid(bar_valid),
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.foo_in(foo_in), .bar_in(bar_in));
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task fail;
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begin
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$display("FAILED -- foo/bar=%b/%b, foo/bar_valid=%b/%b, foo/bar_in=%b/%b",
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foo, bar, foo_valid, bar_valid, foo_in, bar_in);
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$finish;
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end
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endtask // fail
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initial begin
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clk = 0;
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foo_valid = 1;
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bar_valid = 1;
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foo_in = 0;
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bar_in = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (foo !== 0 || bar !== 0)
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fail;
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bar_in = 1;
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#1 clk = 1;
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#1 clk = 0;
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if (foo !== 0 || bar !== 1)
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fail;
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foo_in = 1;
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bar_in = 0;
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foo_valid = 1;
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bar_valid = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (foo !== 1 || bar !== 1)
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fail;
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$display("PASSED");
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end
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endmodule // main
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