34 lines
1.1 KiB
Verilog
34 lines
1.1 KiB
Verilog
/* Copyright (C) 2000 Stephen G. Tell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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* Boston, MA 02111-1307 USA
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*/
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/* fdisplay3 - check that $fdisplay rejects bogus first arguments */
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module fdisplay3;
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initial begin
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// This error is now caught at compile time so this message will not
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// be printed.
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//
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// $display("expect compile or runtime error from bad $fdisplay args:");
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$fdisplay(fdisplay3, "bogus message");
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$finish;
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end // initial begin
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endmodule
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