44 lines
1.3 KiB
Verilog
44 lines
1.3 KiB
Verilog
/* Copyright (C) 2000 Stephen G. Tell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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* Boston, MA 02111-1307 USA
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*/
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/* fdisplay2 - test $fopen and $fdisplay system tasks */
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module fdisplay2;
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integer fp, dfp;
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reg [7:0] a;
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initial begin
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fp = $fopen("work/fdisplay2.out");
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if(fp != 2 && fp != 4 && fp != 8 && fp != 16 && fp != 32 && fp != 64)
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begin
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$display("FAILED fopen fp=%d", fp);
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$finish;
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end
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$fwrite(fp, "hello, world\n");
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a = 8'hac;
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//$fdisplay(1|fp, "a = %h; x: %b\n", a, a^8'h0f);
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dfp = 1|fp;
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$fdisplay(dfp, "a = 'h%h = 'b%b", a, a);
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$finish;
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end // initial begin
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endmodule
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