49 lines
1.2 KiB
Verilog
49 lines
1.2 KiB
Verilog
/*
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* Copyright (c) 2001 Juergen Urban
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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module sensitivity_list ();
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parameter ii = 4;
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reg CLK;
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reg A;
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reg [ii-1:0] B,C;
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initial
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begin
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#30;
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C <= {ii{1'b0}};
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#60;
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$finish(0);
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end
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always
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begin
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CLK = 1'b0;
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#10;
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CLK = 1'b1;
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#10;
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$display ($time);
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end
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always @(A or C) begin
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A = 1'b0;
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$display ("combinatorial process ", A, " time:",$time);
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A = 1'b1;
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$display ("combinatorial process ", A, " time:",$time);
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B = A+C;
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end
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endmodule
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