44 lines
769 B
Verilog
44 lines
769 B
Verilog
module event_array_test();
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event my_event[3:0];
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integer event_count[3:0];
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generate
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genvar i;
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for (i = 0; i < 4; i = i + 1) begin
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always @(my_event[i]) begin
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$display("Got event %d", i);
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event_count[i] = event_count[i] + 1;
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end
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end
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endgenerate
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initial begin
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event_count[0] = 0;
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event_count[1] = 0;
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event_count[2] = 0;
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event_count[3] = 0;
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#1 ->my_event[0];
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#1 ->my_event[1];
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#1 ->my_event[2];
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#1 ->my_event[3];
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#1 ->my_event[1];
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#1 ->my_event[2];
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#1 ->my_event[3];
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#1 ->my_event[2];
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#1 ->my_event[3];
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#1 ->my_event[3];
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#1;
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if ((event_count[0] === 1)
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&& (event_count[1] === 2)
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&& (event_count[2] === 3)
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&& (event_count[3] === 4))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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