55 lines
1.6 KiB
Verilog
55 lines
1.6 KiB
Verilog
/*
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* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This tests the rule in section 2.7.1:
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* "Neither the leading backslash character nor the terminating
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* white space is considered to be part of the identifier. There-
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* fore, an escaped identifier \cpu3 is treated the same as a
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* non escaped identifier cpu3."
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*
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* The cpu3 and \cpu3 notations are for the same object.
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*/
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module top;
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reg \cpu3 ;
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initial begin
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cpu3 = 1;
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$display("cpu3 == %b", \cpu3 );
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if (top.\cpu3 !== cpu3) begin
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$display("FAILED -- top.\\cpu3 !== cpu3");
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$finish;
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end
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if (\top .cpu3 !== \cpu3 ) begin
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$display("FAILED -- \\top .cpu3 !== cpu3");
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$finish;
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end
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if (top.\cpu3 !== 1) begin
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$display("FAILED -- top.\\cpu3 !== 1");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // top
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