10 lines
320 B
Verilog
10 lines
320 B
Verilog
module top;
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// This should be okay (the trimmed bits match the enum MSB).
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enum reg[3:0] {VAL1, XX1='bxxxxx} en1;
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// But these should fail because the trimmed bits do not match the enum MSB.
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enum reg[3:0] {VAL2, XX2='b0xxxx} en2;
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enum reg[3:0] {VAL3, XX3='b0xxxxx} en3;
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initial $display("FAILED");
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endmodule
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