27 lines
379 B
Verilog
27 lines
379 B
Verilog
// Check that it is possible to declare an enum type with a scalar vector type
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// as the base type.
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module test;
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enum reg {
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A
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} e1;
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enum logic {
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B
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} e2;
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enum bit {
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C
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} e3;
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initial begin
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if ($bits(e1) == 1 && $bits(e2) == 1 && $bits(e3) == 1) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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