51 lines
1.4 KiB
Verilog
51 lines
1.4 KiB
Verilog
/*
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* Copyright (c) 2001 Stephan Boettcher <stephan@nevis.columbia.edu>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// $Id: dumpvars.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $
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// $Log: dumpvars.v,v $
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// Revision 1.2 2007/12/06 02:31:10 stevewilliams
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// Clean up work files (caryr)
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//
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// Revision 1.1 2001/07/08 02:56:25 sib4
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// Test for PR#174
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//
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//
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// Test if $dumpvars() accepts non-hierachical names
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module dumptest;
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submod u1(0);
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submod u2(1);
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initial
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begin
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$dumpfile("work/dumptest.vcd");
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$dumpvars(0, dumptest.u1);
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$dumpvars(0, u2);
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$display("PASSED");
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$finish;
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end
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endmodule
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module submod (b);
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input b;
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reg a;
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initial a = b;
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endmodule
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