87 lines
2.1 KiB
Verilog
87 lines
2.1 KiB
Verilog
/*
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* Copyright (c) 2002 Stephen Rowland
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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module dummy7;
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`define ADDR1 16'h0011
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`define ADDR2 16'h0022
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`define ADDR81 8'h11
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`define ADDR82 8'h22
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reg [7:0] data1;
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reg [7:0] data2;
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reg [7:0] data3;
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reg [7:0] data4;
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reg [7:0] addr;
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reg [15:0] addr16;
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// use mod operator to convert literal to 8 bits - this works in verilogXL
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always @ (addr)
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case (addr)
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`ADDR1 %256 : data1 = 8'h11;
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`ADDR2 %256 : data1 = 8'h22;
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default : data1 = 8'h00;
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endcase
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// icarus like this
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always @ (addr)
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case (addr)
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`ADDR1 : data2 = 8'h11;
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`ADDR2 : data2 = 8'h22;
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default : data2 = 8'h00;
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endcase
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always @ (addr16)
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case (addr16)
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`ADDR1 : data3 = 8'h11;
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`ADDR2 : data3 = 8'h22;
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default : data3 = 8'h00;
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endcase
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always @ (addr)
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case (addr)
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`ADDR81 : data4 = 8'h11;
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`ADDR82 : data4 = 8'h22;
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default : data4 = 8'h00;
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endcase
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initial
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begin
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addr = 8'h00;
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addr16 = 16'h0000;
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#10;
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$display("should be 00 -- data1=%h data2=%h data3=%h data4=%h\n",data1,data2,data3,data4);
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addr = 8'h11;
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addr16 = 16'h0011;
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#10;
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$display("should be 11 -- data1=%h data2=%h data3=%h data4=%h\n",data1,data2,data3,data4);
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addr = 8'h22;
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addr16 = 16'h0022;
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#10;
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$display("should be 22 -- data1=%h data2=%h data3=%h data4=%h\n",data1,data2,data3,data4);
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$finish(0);
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end
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endmodule
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