64 lines
1.5 KiB
Verilog
64 lines
1.5 KiB
Verilog
`begin_keywords "1364-2005"
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/*
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* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This tests the behavior of drive strength attached to a buf device.
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* The assign of a reg to the bit should override the value and give a
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* well defined result.
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*/
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module main;
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wire bit;
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PULLDOWN pd(bit);
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reg drv;
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assign bit = drv;
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initial begin
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drv = 0;
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#100 if (bit !== 1'b0) begin
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$display("FAILED -- 0 bit = %b", bit);
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$finish;
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end
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drv = 1;
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#100 if (bit !== 1'b1) begin
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$display("FAILED -- 1 bit = %b", bit);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // main
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module PULLDOWN (O);
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output O;
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wire A;
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pulldown (A);
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buf (weak0,weak1) #(1,1) (O,A);
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endmodule
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`end_keywords
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